The present invention is related to field programmable integrated circuits, and more particularly, to Field Programmable Gate Arrays (FPGAs).
Typically, an FPGA has an array of logic elements and wiring interconnections with many thousands, or even hundreds of thousands, of programmable switches so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable switch, or interconnect, can connect two circuit nodes in the integrated circuit to make (or break) a wiring interconnection, or to set the function or functions of a logic element.
Basic considerations in the architecture of all FPGAs are the complexity of the logic element, and the placement and routing of the wiring interconnecting the arrayed logic elements. A highly complex logic cell may be able to perform a large number of sophisticated operations. However, if a relatively simple operation, such as that of a NOR gate, is required by the FPGA user, much of the functionality and occupied space of the logic cell is wasted. On the other hand, a single transistor as a "logic cell" requires the use of valuable wiring resources to other "logic cells" before any functionality is achieved. Thus a balance must be reached between functionality and flexibility, based upon the likelihood of utilization by the user of the FPGA.
Related to the design of the logic cell in the array is the placement and routing of the wiring in the FPGA. The wiring should be designed so that the likelihood of use of each wiring segment is maximized, yet the use of wiring segments for one purpose should not be a bottleneck to wiring connections for other purposes. Furthermore, the ease of use of the routing of the wiring and the operating speeds of the configured FPGA are other considerations in the design. These factors must be weighed and balanced.
The present invention is a solution to the problem of FPGA architecture design. With the present invention, the logic cell and wiring are designed so that an FPGA with a high degrees of functionality, flexibility, utilization, ease of use and operating speeds is possible. Many of the issues which have plagued FPGA architecture are solved or mitigated.